2025-05-21
14:58 |
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Error-Redundant Implementation of Commercial IP Cores: A Practical Example
/ Jacobsohn, Philipp (speaker) (SmartDV)
The reuse of predefined IP cores is a well-established practice in semiconductor design, offering cost and technical advantages. However, commercial providers must meet diverse implementation requirements, ensuring compliance with specifications while optimizing power, frequency, gate utilization, and feature scope. [...]
2025 - 1371.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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詳細記錄
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2025-05-21
14:58 |
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NDK: An open-source framework for high-speed network applications on FPGAs
/ Iša, Radek (speaker) (CESNET) ; Kondys, Daniel (speaker) (CESNET)
CESNET (Czech Education and Scientific Network) has a long history of providing backbone connectivity and services to institutions such as universities and research centers. One of its subdivisions, tasked with monitoring network traffic, was already familiar with the FPGA technology when 100 GE networks emerged. [...]
2025 - Streaming video.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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詳細記錄
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2025-05-21
14:58 |
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The PandABlocks framework for flexible run-time configuration of Zynq SoCs
/ Christian, Glenn (speaker) (Diamond Light Source)
The PandABlocks framework comprises FPGA gateware, linux kernel and root filesystem for the PS, a TCP server and web-UI. It was originally developed to support the Zynq-7000 based PandABox hardware platform used in beam line scanning applications at several synchrotron light sources for orchestration of motion systems and detectors. [...]
2025 - 1640.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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詳細記錄
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2025-05-21
14:58 |
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Unleashing >100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST
/ Sotiropoulou, Calliope-Louisa (speaker) (CAST)
As modern digital systems demand increasingly higher data rates, the role of high-throughput, low-latency communication becomes critical in applications such as data acquisition, real-time processing, and high-performance computing. This talk describes how UDPIP and TCPIP hardware protocol stack IP cores can be designed to deliver deterministic, line-rate Ethernet communication in FPGA-based systems. [...]
2025 - 1778.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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詳細記錄
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2025-05-21
14:58 |
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Open Logic – open-source FPGA Standard Library
/ Bründler, Oliver (speaker) (OpenLogic)
Open Logic is the fastest-growing open-source HDL standard library on the market, as measured by GitHub stars. It simplifies FPGA development with reusable, modular, and vendor-independent components. [...]
2025 - 2254.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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詳細記錄
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2025-05-21
14:58 |
詳細記錄
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2025-05-21
14:57 |
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2025-05-21
14:50 |
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2025-05-21
14:50 |
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2025-05-21
14:47 |
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