2025-05-22 13:48 |
Notice détaillée
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2025-05-22 13:48 |
Notice détaillée
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2025-05-22 13:41 |
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Distributed Arithmetic for Real-time Neural Networks on FPGAs
/ Sun, Chang (speaker) (California Institute of Technology (US))
Neural networks with a latency requirement at the order of $\mu$s, like the ones used at the CERN Large Hadron Colliders, are typically deployed on FPGAs fully unrolled. A bottleneck for deployment of such neural networks is area utilization, which is directly related to the constant matrix-vector multiplications (CMVM) performed in the networks. [...]
2025 - 1426.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-22 13:41 |
Notice détaillée
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2025-05-22 13:41 |
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A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine
/ Sapkas, Michail (speaker) (Universita e INFN, Padova (IT))
Trying to modulate the RF cavity of a Synchrotron Light Source by leveraging Reinforcement Learning, resulted in a hardware implementation of the Gated Recurrent Unit (GRU) on the Versal AI Engine, by AMD Xilinx and extremely efficient in performing the main numerical operations needed by the model.
RNNs have been designed to handle time series, and they are the perfect candidates to handle this kind of task. Although RNNs don't parallelize well, their ability to distill input and pass information into the hidden state, could be beneficial for real time control tasks.
I will firstly introduce the AI Engine and its features. [...]
2025 - 1584.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-22 13:41 |
Notice détaillée
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2025-05-22 13:41 |
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Exploring Linearity and Temperature Stability in Time-to-Digital Converters
/ Brazerol, Gian-Luca (speaker) (Ostschweizer Fachhochschule)
High-precision time measurements on the order of picoseconds ($10^{-12}$), as required in fluorescence lifetime microscopy and time-of-flight (ToF) applications, can be achieved using Time-to-Digital Converters (TDCs). Traditional timing methods rely on high-frequency clock counters, which become impractical for such small time intervals. [...]
2025 - 1820.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-22 10:17 |
Notice détaillée
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2025-05-22 09:53 |
Notice détaillée
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2025-05-22 09:53 |
Notice détaillée
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