2025-05-22
17:07 |
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HDLRegression: A reliable and efficient tool for FPGA regression testing
/ Elvegård, Marius (speaker) (Inventas)
HDLRegression was developed to provide a reliable, efficient tool for regression testing of maintenance testbenches for UVVM and other FPGA project testbenches. It simplifies simulations with minimal changes—just a single comment in the testbench entity—making it easy to integrate into existing projects.
One big advantage is its independence from any specific verification framework, enabling use with UVVM, OSVVM, VUnit, or any other in-house tools for maximum flexibility.
As FPGA designs grow more complex, numerous tests are needed to verify functionality. [...]
2025 - 1808.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Record dettagliato
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2025-05-22
16:23 |
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Generating memory maps with Cheby and Reksio
/ Gingold, Tristan (speaker) (CERN) ; Bielawski, Bartosz (speaker) (CERN)
Cheby is an HDL tool which transforms a YAML description of a memory map into HDL code, C header, python constants or HTML documentation. The tool was designed to be flexible: it supports many buses, many kinds of peripherals (registers, memories, wires, submodules) as well as structural features like repetition. [...]
2025 - 1484.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Record dettagliato
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2025-05-22
16:23 |
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Allo: A Python-Embedded Programming Model for Composable Accelerator Design
/ Chen, Hongzheng (speaker) (Cornell University)
Special-purpose hardware accelerators are critical for performance gains amid slowing technology scaling, but designers lack effective tools to build complex accelerators. Existing high-level synthesis (HLS) tools require intrusive source-level changes to attain high performance while most accelerator design languages excel only with simple kernels. [...]
2025 - 1725.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Record dettagliato
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2025-05-22
16:03 |
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Customized eFPGAs with FABulous
/ Koch, Dirk (speaker) (Ruprecht-Karls-Universität Heidelberg)
FABulous is an eFPGA (embedded FPGA) framework comprising a full ecosystem for specifying, simulating, emulating and implementing FPGA ASIC macros as well as for providing the corresponding FPGA CAD suite for implementing user designs (the bitstreams) for the custom-defined eFPGAs.
[https://fabulous.readthedocs.io/en/]
This ecosystem integrates a range of open-source tools, including Yosys, nextpnr, Verilator and can use OpenLane and industry tools for the ASIC backend. [...]
2025 - 1753.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Record dettagliato
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2025-05-22
16:03 |
Record dettagliato
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2025-05-22
13:48 |
Record dettagliato
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2025-05-22
13:48 |
Record dettagliato
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2025-05-22
13:41 |
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Distributed Arithmetic for Real-time Neural Networks on FPGAs
/ Sun, Chang (speaker) (California Institute of Technology (US))
Neural networks with a latency requirement at the order of $\mu$s, like the ones used at the CERN Large Hadron Colliders, are typically deployed on FPGAs fully unrolled. A bottleneck for deployment of such neural networks is area utilization, which is directly related to the constant matrix-vector multiplications (CMVM) performed in the networks. [...]
2025 - 1426.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Record dettagliato
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2025-05-22
13:41 |
Record dettagliato
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2025-05-22
13:41 |
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A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine
/ Sapkas, Michail (speaker) (Universita e INFN, Padova (IT))
Trying to modulate the RF cavity of a Synchrotron Light Source by leveraging Reinforcement Learning, resulted in a hardware implementation of the Gated Recurrent Unit (GRU) on the Versal AI Engine, by AMD Xilinx and extremely efficient in performing the main numerical operations needed by the model.
RNNs have been designed to handle time series, and they are the perfect candidates to handle this kind of task. Although RNNs don't parallelize well, their ability to distill input and pass information into the hidden state, could be beneficial for real time control tasks.
I will firstly introduce the AI Engine and its features. [...]
2025 - 1584.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Record dettagliato
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